1. Field of the Invention
The present invention generally relates to integrated circuit dynamic random access memories, and more particularly to trench capacitor construction.
2. Background Description
In dynamic random access memory (DRAM) evolution, reduction in cell area is critical to the development of the next generation and insuring an early cost cross-over. Currently, there are many types of DRAM cells. In the one Giga bit arena demands on capacitance area are great. In addition, DRAM trench cells having transfer device regions bound by deep trenches lend themselves more readily to sub 8 square layout than DRAM trench cells having transfer device regions surrounded by shallow trench isolation oxide.
DRAM trench cells having transfer device regions bound by deep trenches have challenges associated with the strapping capacitor to array device source, which is currently done with a surface strap. Overlay and image size are critical to yield and the strap takes up significant area interfering with array transfer device channel length and preventing the cell from further shrinkage.